![]() The FPGA generates the appropriate number of clock pulses to complete the configuration. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. ![]() The XC17V00 PROM can configure a Xilinx FPGA using the FPGA serial configuration mode interface. See Figure 1 and Figure 2 for simplified block diagrams of the XC17V00 family. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, costeffective method for storing large Xilinx FPGA configuration bitstreams.
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